Integrated circuit (IC) design becomes more challenging as IC technologies continually progress towards smaller feature sizes, such as 32 nanometers, 28 nanometers, 20 nanometers, and below. For example, when fabricating IC devices, IC device performance is seriously influenced by lithography printability capability, which indicates how well a final wafer pattern formed on a wafer corresponds with a target wafer pattern defined by an IC design layout. Various methods (such as optical proximity correction (OPC), mask proximity correction (MPC), and inverse lithography technology (ILT)) have been introduced for enhancing lithography printability, which focus on optimizing a mask used for projecting an image that corresponds with the target wafer pattern on the wafer. However, lithography printing capability is also limited by the wafer fabrication process itself, which uses the optimized mask. Although existing methods for enhancing lithography printability have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects